An Efficient Constant Multiplier Architecture Using 8 Bit Binary Common Sub-expression Elimination
نویسنده
چکیده
FIR filters are widely used in digital signal processing, image processing, wireless communication and software defined radio. In SDR, reconfigurable FIR filter with dynamically programmable filter coefficients are essential. In FIR filter, the multiplication is performed between one particular variable (the input) and many constants (the coefficients) and known as multiple constant multiplications (MCM). An efficient VHBCSE algorithm for FIR filter is adopted for 4 bit as well as 8 bit common subexpression elimination.4 bit BCSE is applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially followed by applying variable-bit BCSE algorithm horizontally within each coefficient. Main objectives of this algorithm are, to reduce the average switching activity of the multiplier and adder blocks and to reduce the power consumption along with an improvement in the
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